As is well known to those skilled in the art, delta sigma analogue to digital converters (ADC) offer high tolerance to analogue component imperfections with high performance, reduced differential non-linearity errors, and reduce the need for complex anti-aliasing filters in comparison to other ADC implementations. For these and other reasons delta sigma ADCs have become a popular choice for low to moderate frequency, high resolution applications.
Delta sigma ADCs can be implemented either in Continuous-Time (CT) or Switched-Capacitor (SC) configurations, each having its own advantages and disadvantages which will be familiar to those skilled in the art. At the circuit level delta sigma ADCs can be realised in fully differential of single-ended variants. Fully differential variants are usually preferred, as they provide greater linearity, lower noise and better common-mode and power supply rejection properties.
In some applications it is necessary or advantageous to use a single-ended ADC, for example where the input to the ADC is a microphone or audio line in input. In such applications it is common to convert a fully differential delta sigma ADC into a single-ended delta-sigma ADC, typically by using a single-ended to differential converter (SDC) whose input receives the single-ended input, and whose differential outputs are fed to the differential inputs of a differential delta sigma ADC, as is shown in FIG. 1. This approach imposes stringent requirements on the SDC, as to avoid degrading the linearity and noise performance of the delta sigma ADC the SDC must have better linearity and noise characteristics than the delta sigma ADC.
To solve this problem the SDC can be moved inside the negative feedback loop of the delta sigma ADC, as is shown in FIG. 2. This reduces the problem of non-linearity, as the negative feedback loop of the delta sigma ADC strives constantly to make the digital output of the delta sigma ADC as close as possible to its analogue input.
However, the SDC is a high power component which increases the overall power consumption of the delta sigma ADC. Thus, this approach is not suitable for low-power applications.
A lower power alternative is illustrated in FIG. 3. In this system a differential delta sigma ADC is used in a single-ended mode with one of its inputs connected to a constant voltage reference such as ground. Although this arrangement offers reduced power consumption in comparison to the arrangements shown in FIGS. 1 and 2, it suffers from poor linearity and harmonic distortion performance, as its inputs are no longer at a virtual ground potential, which permits a signal swing to develop at these inputs. This signal swing distorts the output of the delta sigma ADC, reducing linearity and degrading harmonic distortion performance.